Field of the Invention
The invention relates to a memory module, in particular a semiconductor memory. The memory module has a substrate, in which memory cells are formed. The memory cells each have a capacitor and a selection transistor. A memory cell is connectable to a bit line through the selection transistor. Word lines are provided, by which the selection transistors can be switched in order to read out and/or write in an item of information stored in the memory cell via the bit line. The capacitor has a first electrode and a counter electrode, the counter electrode being formed as an electrically conductive region in the substrate. The first electrode is electrically conductively connected to the selection transistor. The memory cells are provided for storing and outputting items of information and are disposed in an active region of the substrate. Dummy memory cells are formed in a manner adjoining the active region. The dummy memory cells are not used for storing items of information. A dummy memory cell has a first electrode and a counter electrode, the counter electrode is formed as an electrically conductive region in the substrate. The counter electrode is connectable to a voltage potential.
Semiconductor memories are used for example as dynamic semiconductor memories (DRAMs) in order to enable fast and cost-effective storage of items of information. The further development in the case of semiconductor memories leads, in the case of new memory generations, to ever shorter activation times of the word lines (row cycle time), ever longer word line lengths and an increase in the parallelism in the case of read accesses. This is manifested particularly in the case of prefetch instructions of a double data rate DRAM. If the content of a DRAM is rewritten, this results in that the charge is changed in the capacitors of the memory cells situated in parallel in the substrate of the memory. If the sign of a change in charge is not statistically distributed, rather the same voltage is written to the majority of the memory cell capacitors, then the result is a significant entry of charge into the counter electrode of the memory cells, which is formed in the substrate. The overall result is an alteration of the voltage in the counter electrode. This change in voltage must be compensated for as a displacement current from the on-chip voltage supply network. The magnitude of the displacement current is proportional to the charge of the memory cell capacitors that is rewritten per unit time.
The facts described mean that it is becoming increasingly difficult to stabilize the potential of the counter electrode. The electrical connection between the counter electrode and a voltage generator, which is intended to stabilize the network of the counter electrode, is formed in the form of metal tracks and well contacts. The metal tracks and well contacts have a non-negligible electrical resistance. As a result, even with an adequately dimensioned voltage generator, the charge required for the voltage compensation is not immediately supplied into the counter electrode. However, an unstable potential of the counter electrode leads to shifts in the signal distance between the voltage charged in the capacitor of a memory cell and the voltage of the counter electrode.
It is accordingly an object of the invention to provide a memory module with improved electrical properties which overcomes the above-mentioned disadvantages of the prior art devices of this general type, which has improved stabilization of the voltage potential of the counter electrode of a memory module.
With the foregoing and other objects in view there is provided, in accordance with the invention, a memory module.
The memory module contains a substrate having an active region, a voltage generator outputting a reference potential, and memory cells formed in the substrate and having capacitors and selection transistors. Each of the capacitors has a first electrode and a second electrode being a counter electrode, and the counter electrode is an electrically conductive region disposed in the substrate. The first electrode is electrically conductively connected to a respective one of the selection transistors. The memory cells store and output items of information and are disposed in the active region of the substrate. Dummy memory cells are disposed adjoining the active region, the dummy memory cells are not used for storing items of information. Each of the dummy memory cells has a first dummy electrode and a second dummy electrode being a counter dummy electrode. The counter dummy electrode is an electrically conductive region disposed in the substrate. The counter dummy electrode is connectable to a voltage potential. The first dummy electrode is electrically conductively connected to the voltage generator outputting the reference potential. Bit lines are connected to the selection transistors for accessing the memory cells. Word lines are connected to and drive the selection transistors for reading out and/or writing in the items of information stored in the memory cells through the bit lines.
An essential advantage of the invention is that the electrical capacitance of dummy memory cells is used to increase the capacitance of the counter electrode. Dummy memory cells are provided in a multiplicity of embodiments of memory modules in order to form symmetrically boundary regions of the configuration of the memory cells as far as possible identically with inner regions of the configuration of the memory cells. Hitherto, the first electrodes of the dummy memory cells have not been connected to a fixed potential, but rather have been floating. In the memory module according to the invention, in contrast, the first electrodes of the dummy memory cells are electrically conductively connected to a voltage potential (e.g. GND). As a result, an electrical capacitance that is already present on the memory module is coupled to the counter electrode and the total capacitance of the counter electrode is thus increased. As a result, the counter electrode becomes less sensitive overall with respect to excessively large entries of charge, since, with an increased capacitance, even relatively large entries of charge can be compensated for without excessively large changes in voltage.
In one preferred embodiment, dummy word lines are disposed above the dummy memory cells, which dummy word lines are preferably electrically conductively connected to the first electrodes of the dummy memory cells and to a voltage potential or network (e.g. GND). Consequently, besides the capacitance of the dummy memory cell, at the same time the capacitance of the dummy word line is utilized as an additional capacitance for the counter electrode. Consequently, the capacitance of the counter electrode is increased still further without having to carry out significant changes in the layout in comparison with previous customary configurations of dummy memory cells.
In a further advantageous embodiment, the first electrodes of the dummy memory cells are electrically conductively connected to one another, and are electrically conductively connected to a voltage potential or network (e.g. GND), via an electrically conductive track that is introduced into the substrate. Consequently, a further embodiment is provided which enables a simple and cost-effective connection of the first electrodes of the dummy memory cells to the voltage network. In this embodiment, the capacitance of the counter electrode is additionally increased not only by the capacitance of the dummy memory cells but also by the capacitance of the electrically conductive track. This embodiment has the disadvantage that an additional electrically conductive track has to be introduced into the substrate. However, this embodiment has the advantage that the capacitance of the counter electrode not only increases through the capacitances of the dummy memory cells, but also increases through the capacitance of the electrically conductive track. Consequently, overall an additional increase in the capacitance of the counter electrode is achieved.
A further improvement of the memory module is achieved by virtue of the fact that further dummy memory cells whose first electrodes are floating, i.e. electrically insulated, are disposed in a manner adjoining dummy memory cells which are electrically conductively connected to the voltage network. What is achieved by this embodiment is that even when the dummy memory cells are connected to the voltage network, the edge regions of the dummy memory cells are situated in an environment similar to inner regions of the memory cell configuration. In this way, dummy memory cells that are electrically conductively connected to the voltage network are at least partly shielded from disturbing edge effects. Consequently, an entry of disturbing effects via the dummy memory cells into the counter electrode is largely avoided.
In a further preferred embodiment, further dummy memory cells whose first electrodes are electrically insulated are disposed between the memory cells and the dummy memory cells. This embodiment has the advantage that the layout that has been customary hitherto only has to be supplemented and there is no need to change the previous method.
In accordance with an added feature of the invention, an electrically conductive track structure is disposed in the substrate and has a longitudinal track. The longitudinal track is disposed parallel to the dummy word lines and the word lines. The electrically conductive track structure has transverse tracks disposed perpendicularly to the longitudinal track, and the transverse tracks are electrically conductively connected to the longitudinal track. The further dummy memory cells are disposed in a same grid as the dummy memory cells, and the further dummy memory cells have first further electrodes electrically conductively connected to one another through the electrically conductive track structure. Each of the transverse tracks are electrically conductively connected to the first dummy electrodes of in each case two of the further dummy memory cells of the active region. The further dummy memory cells are disposed remote from the longitudinal track, and the electrically conductive track structure is electrically conductively connected to the voltage generator.
In accordance with a further feature of the invention, a conductive layer is disposed in the substrate. In each case two of the first dummy electrodes of two of the dummy memory cells are electrically conductively connected to one another through the conductive layer. In addition, an electrically conductive contact is connected to the dummy word line and is disposed directly above the conductive layer.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a memory module with improved electrical properties, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.